The present invention relates to a timing signal generator for use in a digital video signal processor.
Large scale integrated circuit (LSI) technology has so significantly developed that a signal processor capable of processing digital signals in the audio band on a real time basis is already available in a single-chip LSI. A problem, however, in implementing a processor for real time processing of video signals, having a band some 1,000 times as wide as audio signals, lies the fact in that the processing speed of the device cannot readily be increased 1,000 times. A conceivable solution is to achieve such 1,000 times faster processing would be to use a plurality of processors, each having a speed comparable to the processor for audio band signals and having them operate in parallel. An example of such a processor is described in European Patent Application No. A2 0169709 (corresponding to U.S. patent application Ser. No. 756,027 filed on July 17, 1985) published on Jan. 29, 1986. This processor, comprising a plurality of unit processors, divides a frame of video signals into a plurality of picture blocks, and each unit processor processes the picture block assigned to it. The picture blocks to be processed and outputted by the unit processors are so allocated that the output picture block of each unit processor neither overlaps with nor has a gap between itself and the output picture block of any other unit processor. Accordingly, the final processed frame is obtained by synthesizing the output picture blocks from the plurality of unit processors. Meanwhile, since the input block in each unit processor is set greater than the area of the picture block assigned to it, communication between the individual unit processors can be virtually nil. Thus, the picture block to be inputted is greater than that of the output picture block.
In such a multi-processor arrangement, each unit processor requires a timing signal generator or the like for generating signals indicating the areas of input picture blocks, the areas of output picture blocks and the start of processing by each unit processor.
As mentioned above since the input and output areas assigned to a unit processor the next are different with each unit processor, the timing signal is also different in each processor. Thus although all unit processors share a common overall structure, LSI implementation of the unit processors difficult is because the timing signal generator of each unit processor is different.
Moreover, it may also become necessary, depending on the digital signal processing method that is applied, to vary the sizes of the input and output picture blocks, or to alter the positions of the input and output picture blocks according to the result of digital signal processing. These needs can be met by storing in a random access memory (RAM) addresses of the input and output picture blocks that have to be changed. However, since the use of a RAM entails too long a time in transferring the pertinent data the use of such a RAM is not preferable in a processor which has to process digital signals at high speed.